Nonvolatile memory (NVM) cells retain stored information without receiving a constant or persistent power supply. NVM cells can provide significant power savings for electronic systems that do not need or provide constant power to the cells. Also, the initialization time for electronic systems can be reduced via NVM. For example, instructions stored in an NVM cell are ready to execute and do not need to be recreated or reloaded during the initialization process.
NVM cells generally store information in a digital format. For example, NVM cells store information as zeros or ones. Hence, NVM cells generally toggle between a first state and a second state to reflect the digital format. The states may include an electrical charge state (e.g., Flash memory) or a magnetic state (e.g., Spin-Torque Transfer magnetoresistive random access memory (STT-RAM)).
Generally, an STT-MRAM cell includes a magnetic tunnel junction (MTJ) that acts a storage structure for a bit of information. The MTJ is toggled between different states using an NMOS transistor that provides a drive current to the MTJ that changes the spin of the electrons within a portion of the MTJ, such that the STT-MRAM cell can exist in at least two different magnetoresistive states for extended periods without a constant or persistent power supply. For example, the first state may be a zero state and the second state being a one state, such that each state may be read as a digital bit. The amount of drive current needed to transition the MTJ between the two states may be asymmetrical. In short, more drive current may be used to transition the MTJ from the first state to the second state, than the drive current used to transition the MTJ from the second state back to the first state.
In a NMOS transistor MRAM cell, the higher current state places the MTJ and the NMOS transistor in non-optimal operating conditions. For example, the higher current state can impact the reliability of the MTJ and it subjects the NMOS transistor to higher body effects. Hence, both components are operating at a less than optimal state or condition at the same time. Also, the higher current requirement dictates the size of the NMOS transistor and limits the scalability of the MRAM cell to smaller geometries.